The preferred embodiments relate to integrated circuit capacitor measurement and testing.
The controlled and successful manufacture of integrated circuits requires evaluations, including measurement, testing, reliability, and predictability of various parameters and behavior in the manufactured devices. One particular parameter example is capacitance, including the capacitance of structures that are intended to be capacitors in the circuit function itself. Variations in capacitance may be affected or caused by manufacturing variations, temperature dependence, voltage dependence, device structure, and other manufacturing parameters and operating conditions, both in a given structure and over a population of manufactured integrated circuits, including variations in capacitance among capacitors within a given integrated circuit.
Capacitance variations and capacitor mismatch have been addressed in the design of modern analog-to-digital converters. Examples of calibration and correction techniques are described in U.S. Pat. No. 7,136,006, U.S. Pat. Nos. 6,891,486, and 8,686,744, all three of which are commonly assigned herewith, and in Tan et al., “Error Correction Techniques for High-Performance Differential A/D Converters”, J. Solid-State Circ., Vol. 25, No. 6 (IEEE, 1990), pp. 1318-27, all of which are incorporated herein by reference.
For purposes of calibration, trimming, and process control, it is useful to measure capacitor behavior in manufactured devices, for example in wafer form along with functional and parametric electrical test. Additionally for such purposes, and for additional considerations such as circuit longevity, viability, and operational limit determination, stress testing of circuit elements also may be useful. Such combined aspects, therefore, are considerations addressed by the preferred embodiments.
By way of background to certain of the above considerations, FIG. 1 illustrates a conventional circuit for measuring mismatch between capacitors C1 and C2, that is, by evaluating the capacitance of one (or each) capacitor relative to the other. Capacitors C1 and C2 are connected in series between terminals V1 and V2. In practice, capacitor C2 may be a “reference” capacitor, against which the capacitance of capacitor C1 is to be measured. A node VINT between capacitors C1 and C2 is connected to the gate of a p-channel metal-oxide-semiconductor (MOS) transistor 14, the drain of which is at ground and the source of which is connected through a current source 12 to a bias voltage VDD. The body of transistor 14 is connected to its source, in this example.
In operation, current source 12 is biased to produce a constant current I1, and bias voltage VDD is sufficiently positive (relative to the ground voltage at the drain of transistor 14) to place transistor 14 in saturation. As well-known in the art, transistor 14 operates as a “source follower” under those conditions; because transistor 14 is in saturation, the constant source-drain current I1 forces the transistor gate-to-source voltage VGS to be constant. As such, ideally output voltage VOUT (or, designated over time, VOUT(t)) at the source of transistor 14 follows changes in the voltage at its gate, which is at node VINT.
To perform measurement of the relative capacitances of capacitors C1 and C2, the voltage at node V2 is held constant (e.g., at ground) and the voltage at node V1 is ramped over time, that is, increased linearly from a starting voltage (e.g., ground) to a higher voltage. The voltage at intermediate node VINT will respond to the ramped voltage V1 by also ramping, but at a flatter slope according to the voltage divider of capacitors C1 and C2, as shown in Equation 1:
                                          V            INT                    ⁡                      (            t            )                          =                  V          ⁢                                          ⁢          1          ⁢                                    (              t              )                        ·                          (                                                C                  1                                                                      C                    1                                    +                                      C                    2                                                              )                                                          Equation        ⁢                                  ⁢        1            In other words, Equation 1 defines the slope the expected increasing voltage at node VINT as
      (                  C        1                              C          1                +                  C          2                      )    .Moreover, and also ideally, the slope of the output voltage VOUT from the source follower of transistor 14 increases with this same slope as the ramping voltage VINT(t), that is, the expected slope for the rise of VOUT is as shown in Equation 2:
                    S        =                              C            1                                              C              1                        +                          C              2                                                          Equation        ⁢                                  ⁢        2            
As a result of the preceding, in response to the ramped voltage at node V1, the voltage VOUT(t) may be measured and its slope determined, from which the capacitances of capacitors C1 and C2 can be determined according to the following Equation 3:
                                          C            2                                C            1                          =                              (                          1              -              S                        )                    S                                    Equation        ⁢                                  ⁢        3            
From Equation 3, therefore, if nominally the capacitances of capacitors C1 and C2 are equal, then ideally the ratio of Equation 3 will equal one; or, if the nominal capacitances are accurate, then the ideal ratio thereof should be confirmed by that Equation and by evaluating the slope of VOUT(t). In practice, however, the behavior of the source follower circuit of FIG. 1 is not ideal, especially in modern sub-micron transistors. In the circuit of FIG. 1, the drain-to-source voltage of transistor 14 changes as the voltage at node VINT (and VOUT, at the transistor source) increases. This modulation of the drain-to-source voltage causes some of the changes in the gate voltage to be consumed in charging or discharging parasitic junction capacitances in the device. Furthermore, due to the mechanism of drain-induced barrier lowering, transistor threshold voltages modulate in response to changes in drain-to-body node voltage. These effects cause the slope of output voltage VOUT(t) to not solely reflect the relative capacitances of capacitors C1 and C2, but the ratio also will reflect capacitive effects and also variations in the threshold voltage of transistor 14 over the duration of the measurement. The resulting output voltage VOUT(t) will thus include non-linearities, which can be substantial. The resulting inaccuracy in capacitance measurement is incompatible with capacitors such as those intended for certain precision circuits.
In consideration of certain of the above, and co-owned with the present patent application, one skilled in the art is invited to review U.S. Pat. No. 8,686,744, which is hereby incorporated herein by reference. This U.S. Pat. No. 8,686,744 describes at least one preferred embodiment that also connects a node, existing between two series-connected capacitors, to a source follower transistor configuration, for purposes of testing for a mismatch in the capacitance value of the two capacitors. More specifically, a first ramping voltage source is applied across the two capacitors, while a second ramping voltage source, which increases at one half the rate of the first voltage source, is applied to the drain of the source follower. At the same time, the output of the source follower is monitored, which will provide a first slope proportional to a first of the two capacitors. The ratio, therefore, of the first slope to the second slope may be evaluated to determine whether there is a match of the capacitance value of the two capacitors.
By way of further background, capacitor reliability is an additional consideration in circuit design, use, and for purposes of establishing operational specifications. Various models and testing have been used in view of these considerations, where certain such models are typically based on dielectric breakdown. Testing also is sometimes attempted, but accurate measurement of small capacitance shift under electrical stress is difficult and there is very limited data available on how capacitors degrade over time.
Given the preceding, the present inventors have identified numerous limitations and potential improvements to the prior art, as are further detailed below.